Thin-film transistors (TFT) made of amorphous silicon for selecting pixels are used in a pixel circuit in an active-matrix liquid crystal display or an organic EL display. In order to drive the selecting TFTs, a driver circuit is provided at a periphery of the display. The driver circuit is composed of a logic device for outputting a driving pulse for turning the selecting TFT on or off.
The selecting TFTs are provided at intersections of scanning lines and data lines. The driver circuit turns on the selecting TFTs in the pixel row selected through the scanning lines, such that data signals from the signal line is written on each of the pixels, or the pixels emit light. Shift register is a driver circuit which outputs a selection signal for each of the selected pixel rows. The patent literature 1 discloses a specific circuit configuration of the shift register composed of only TFTs having single polarity.
FIG. 11A is a block configuration diagram of a shift resister disclosed in the patent literature 1. The conventional shift register disclosed in FIG. 11A is used as a scanning line selector for the liquid crystal display. The shift register includes multiple stages having nearly identical circuit configuration connected by cascade connection. An output signal from an upper stage is an input signal of the shift register, and the output signal from the shift register is the input signal to another shift register in the lower stage. Three clock signal lines are connected to a clock signal generator 522, and two of the three clock signal lines are connected to each stage.
FIG. 11B is a specific circuit configuration diagram of the stage included in the shift register disclosed in the patent literature 1. The stage 510 in FIG. 11B includes TFTs 516 to 521. All of the TFTs are of the same conduction type. FIG. 12A is an example of a driving timing chart for a case in which the shift register disclosed in the patent literature 1 uses two horizontal periods as an output period. The stage 510 converts the input signal and outputs the output signal from the output 1 by a bootstrapping operation using a clock signal C1. A starting timing for outputting a turn-on voltage which is a selection signal from the output 1 is when the input signal and the clock signal C1 are on, and an ending timing for the output is when the clock signal C1 changes to the off state and the clock signal C3 are on. In the same manner, in the stage 510 which is on the second row, the starting timing for outputting the turn-on voltage from an output 2 is when the signal from the output 1 and the clock signal C2 are on, and an ending timing for the output is when the clock signal C2 is off and the clock signal C1 is on. To put it differently, in the shift register illustrated in the patent literature 1, a scanning line selection with a transfer amount for one horizontal period or for two horizontal periods is enabled by having an on-period for two horizontal periods which is the same as the on-period of the input signal and by using three clock signals having a shift amount for one horizontal period.